One of the difficult areas in the development of any modern hardware system is the production-testing of the Printed Circuit Boards (PCBs). This is the problem addressed by the IEEE standard number 1149 "Standard Test Access Port and Boundary-Scan Architecture". This standards defines a 5-pin serial protocol for accessing and controlling the signal-levels on the pins of a digital circuit, and has some extensions for testing the internal circuitry on the chip itself (which will not be discussed here). The standard was written by the Joint Test Action Group (JTAG) and the architecture defined by it is known as "JTAG boundary scan" or as "IEEE 1149".
The general structure of the JTAG boundary scan test interface is shown in the following figure
